1. Field of the Invention
The present invention relates to a technique for allocating resources in a computer system and particularly to allocating computer bus device resources to a priority requester and retrying requests from non-priority requesters.
2. Description of the Related Art
Business-critical applications continue to demand greater bandwidth and shorter response times from the input/output (I/O) subsystems of computers. As faster and more complex I/O devices, such as Gigabit Ethernet, Fibre Channel, Ultra3 SCSI, and multi-port network interface controllers (NICs) appear on the market, conventional PCI bus technology operating at 33 MHz frequently becomes a performance bottleneck.
At the same time, the computing model is demanding more scalability, availability, and reliability as the enterprise becomes more distributed. To fulfill these needs, high-bandwidth architectures such as system area networks are emerging. System area networks are used to connect distributed resources such as clustered servers, I/O, and storage. Using the PCI bus as a backbone interconnect for these high-bandwidth system architectures can stretch the PCI bus to its limit.
Optimal system performance requires a balance between the processor-to-memory subsystem and the I/O subsystem. Since the introduction of the PCI bus in 1992, the internal clock frequencies of processors have increased dramatically, from less than 100 MHz to more than 1 gigahertz (GHz). The processor-to-memory bus (front-side bus) is now 64 bits wide and operates in the range of 100 to 333 MHz for X86 and Alpha processors. Although the 64-bit, 66-MHz PCI extension exists, the PCI frequency remains at 33 MHz for the vast majority of systems and adapters.
To break this I/O bottleneck, both system and I/O adapter designers are migrating their designs to the 64-bit, 33-MHz PCI bus, which provides a peak bandwidth of 266 megabytes per second (MB/s). The PCI Local Bus Specification Revision 2.2, published by the PCI SIG, a copy of which is incorporated by reference, allows a 66-MHz PCI bus. However, the specification has many technical design challenges that have slowed its implementation. Even when system designers overcome these challenges, the 66-MHz PCI bus at its peak bandwidth of 533 MB/s is not adequate for long-term needs such as multi-port NICs with Gigabit Ethernet. For example, a four-port Gigabit Ethernet NIC, with each port capable of 1 gigabit per second, or 125 MB/s, would overwhelm the 64-bit, 66-MHz PCI bus bandwidth by using essentially all available bandwidth.
Several vendors, including Compaq Computer Corporation, Hewlett-Packard, Inc., and IBM Corp., collaborated to produce the PCI-X specification. PCI-X technology leverages the wide acceptance of the PCI bus and provides an evolutionary I/O upgrade to conventional PCI. PCI-X technology increases bus capacity to more than eight times the conventional PCI bus bandwidth—from 133 MB/s with the 32-bit, 33-MHz PCI bus to 1066 MB/s with the 64-bit, 133-MHz PCI-X bus. It enhances the PCI protocol to develop an industry-standard interconnect that exceeds a raw bandwidth of 1 gigabyte per second (GB/s) and will meet upcoming bandwidth needs of enterprise computing systems. PCI-X provides backward compatibility with the PCI bus at both the adapter and system level.
The conventional PCI protocol supports delayed transactions. With a delayed transaction, a device requesting data must poll a target to determine when the request has been completed and its data is available. The PCI-X protocol replaces delayed transactions with split transactions. With a split transaction as supported in PCI-X, the device requesting the data sends a request to the target. The target device informs the requester that it has accepted the request. The requester is free to process other information until the target device initiates a new transaction and sends the data to the requester. Thus, split transactions enable more efficient use of the bus. Devices such as host bridges that are routinely addressed by multiple other devices are encouraged to complete multiple split transactions concurrently.
If an application benefits from completing multiple transactions of one type concurrently but not others, the device might continue to accept and execute some non-posted transactions and terminate others with retry. For example, if a device is designed to complete multiple memory read DWORD transactions concurrently, but only a single configuration read transaction, the device would signal Split Response to the first memory read DWORD transaction and the first configuration read DWORD transaction. The device would signal Split Response to a subsequent memory read DWORD transaction that was received before the device executed the Split Completion for the first transaction. However, the device would signal retry if it received a subsequent configuration read before the device executed the Split Completion for the first one.
Resources on the target device are typically dedicated to split transactions to allow the target device to process multiple split transactions. Supporting multiple pending split transactions allows more efficient use of the bus and target resources. However, if multiple requesters or initiators attempt to perform transactions with the same target device simultaneously or close in time, some initiator devices can be starved, receiving retry responses to transaction requests if other initiator devices are allocated target device resources each time those resources become available.